1. Field of the Invention
The present invention relates to the design of circuitry within computer systems. More specifically, the present invention relates to a method and an apparatus for reducing the number of pins on semiconductor chips, which are required to communicate address and control signals to memory modules within a computer system.
2. Related Art
As processor clock speeds continue to increase at an exponential rate, larger amounts of data are being transferred at correspondingly faster rates between processor and memory. To accomplish this, computer system designers are beginning to user wider data buses to carry more data as well as wider address buses to address larger amounts of memory. These wider buses can greatly increase the number of signal lines between processor and memory.
Furthermore, as more memory modules are incorporated into computer systems to accommodate larger amounts of code and data, additional address signals and memory control signals (such as chip-select (CS) signals, clock-enable (CKE) signals, and on-die termination (ODT) signals) must be added to support the extra memory modules. This further increases the number of signal lines between processor and memory.
Additionally, more drivers are required to drive the address and control signals to the additional memory modules. These additional drivers typically require more power and ground pins on the semiconductor chips that contain the drivers.
In fact, all of the above-described factors increase the required number of pins on processor chips, bridge chips, and associated buffer chips, to communicate signals between processor and memory. Unfortunately, these chips are typically “pad-limited parts,” which means that the number of I/O pins determines the die size and also affects the package size. Consequently, adding more pins increases the die size and necessitates using larger and more expensive pin-grid array packages, which can greatly increase cost.
Hence, what is needed is a method and an apparatus for reducing the number of pins, which are required to communicate address and control signals to memory modules within a computer system.
Furthermore, using additional drivers to drive address and control signals to additional memory modules can increase the amount of skew in these address and control signals. This additional skew can increase the amount of time required to synchronize address and control signals at the memory modules, which can greatly increase the time required to perform memory operations.
Hence, what is needed is a method and an apparatus for reducing the amount of time required to synchronize address and control signals received at memory modules.